LTC4260IUH#PBF【PDF 8/30 页】IC HOT SWAP CNTRL I2C 32-QFN

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Sheet目录42

4页 5页 6页 7页 [8页]9页 10页 11页 12页

LTC4260

4260fc

For more information www.linear.com/LTC4260

pin FuncTions

ADIN: ADC Input. A voltage between 0V and 2.56V applied

to this pin can be measured by the onboard ADC. Tie to

ground if unused.

ADR0 to ADR2: Serial Bus Address Inputs. Tying these

pins to ground, open or INTV

configures one of 27 pos-

sible addresses. See Table 1 in Applications Information.

ALERT: Fault Alert Output. Open-drain logic output that can

be pulled to ground when a fault occurs to alert the host

controller. A fault alert is enabled by the ALERT register.

This device is compatible with SMBus alert protocol. See

Applications Information. Tie to ground if unused.

BD_PRST: Board Present Input. Ground this pin to en-

able the N-channel FET to turn on after 100ms debounce

delay. When this pin is high, the FET is off. An internal

10礎 current source pulls up this pin. Transitions on this

pin will be recorded in the FAULT register. A high-to-low

transition activates the logic to read the state of the ON

pin and clear Faults. See Applications Information.

Exposed Pad (Pin 33, UH Package): Exposed pad may

be left open or connected to device ground.

FB: Foldback and Power Good Input. A resistive divider

from the output voltage is tied to this pin. When the

voltage at this pin drops below 3.41V, the output power

is considered bad and the current limit is reduced. The

power bad condition can be indicated with the GPIO pin

and a power bad fault can be logged in this condition. See

Applications Information.

GATE: Gate Drive for External N-Channel FET. An internal

18礎 current source charges the gate of the external

N-channel MOSFET. A resistor and capacitor network from

this pin to ground sets the turn-on rate and compensates

the active current limit. During turn-off there is a 1mA

pull-down current. During a short circuit or undervoltage

lockout (V

or INTV

), a 600mA pull-down current

source between GATE and SOURCE is activated.

GND: Device Ground.

GPIO: General Purpose Input/Output. Open-drain logic

output and logic input. Defaults to pull low to indicate

power is bad. Configure according to Table 3.

INTV

: Internal Low Voltage Supply Decoupling Output.

Connect a 0.1礔 capacitor from this pin to ground. This

pin can be used to drive the other pins to logic high and

has an undervoltage lockout threshold of 3.8V.

NC: No Connect. Unconnected pins. These pins provide

extra distance between high and low voltage pins.

ON: On Control Input. A rising edge turns on the external

N-channel FET and a falling edge turns it off. This pin is

also used to configure the state of the FET ON bit (and

hence the external FET) at power up. For example if the

ON pin is tied high, then the FET ON control bit (A3) will

go high 100ms after power-up. Likewise if the ON pin is

tied low then the part will remain off after power-up until

the FET ON control bit is set high using the I

C bus. A

high-to-low transition on this pin will clear faults.

OV (GN/UH Packages): Overvoltage Comparator Input.

Connect this pin to an external resistive divider from V

If the voltage at this pin rises above 3.5V, an overvoltage

fault is detected and the switch turns off. Tie to GND if

unused.

SCL: Serial Bus Clock Input. Data at the SDA pin is shifted

in or out on rising edges of SCL. This is a high impedance

pin that is generally driven by an open-collector output

from a master controller. An external pull-up resistor or

current source is required.

SDAI: Serial Bus Data Input. A high impedance input used

for shifting in address, command or data bits. Normally

tied to SDAO to form the SDA line.

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